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KH104
DC to 1.1GHz Linear Amplifier
Features
s s s s s s
General Description
The KH104 linear amplifier represents a significant advance in linear amplifiers. Proprietary design techniques have yielded an amplifier with 14dB of gain and a -3dB bandwidth of DC to 1100MHz. Gain flatness to 750MHz of 0.4dB coupled with excellent VSWR and phase linearity gives outstanding pulse fidelity and low signal distortion. Designed for 50 systems, the KH104 is very easy to use, requiring only properly bypassed power supplies for operation. This translates to time and cost savings in all stages of design and production. Fast rise time, low overshoot and linear phase make the KH104 ideal for high speed pulse amplification. These properties plus low distortion combine to produce an amplifier well suited to many communications applications. With a 1.1GHz bandwidth, the KH104 can handle the fastest digital traffic, even when the demodulation scheme or the digital coding format requires that DC be maintained. It is also ideal for traditional video amplifier applications such as radar or wideband analog communications systems. These same characteristics make the KH104 an excellent choice for use in fiber optics systems, on either the transmitting or receiving end of the fiber. The low group delay distortion insures that pulse integrity will be maintained. As a photomultiplier tube preamp, its fast response and quick overload recovery provide for superior system performance. The KH104 is constructed using thin film resistor/ bipolar transistor technology, and is available in the following versions: KH104AI
14 +VR
-3dB bandwidth of 1.1GHz 325psec rise and fall times 14dB gain, 50 input and output Low distortion, linear phase 1.4:1 VSWR (output, DC-1.1GHz) Direct replacement for CLC104
Applications
s s s s
Digital and wideband analog communications Radar, IF and RF processors Fiber optic drivers and receivers Photomultiplier preamplifiers
Basic Circuit Diagram
+15V 39 0.01 +15V 2.2 10K Offset Adjust -15V Vin 0.01 0.01
12 4 3,5-10 14 1
KH104
2 13
11
Vo
0.01 2.2
Capacitance if F 39 0.01 -15V
Equivalent Circuit Diagram
+VCC 1
+5.4V Reg
Offset Adjust 12 Vin Ground 4
-25C to +85C
14-pin double-wide DIP
KH104
11 Vo 13 -VR
*
-5.4V Reg
2
*Pins 3, 5-10 case is ground
REV. 1A February 2001
DATA SHEET
KH104
KH104 Electrical Characteristics
PARAMETERS Ambient Temperature FREQUENCY DOMAIN RESPONSE -3dB bandwidth

(TA = +25C, VCC = 15V, RL = 50, Rs = 50; unless specified) TYP +25C 1100 1050 14.2 0.4 1.5 600 40 35 18 11 17 10 325 375 1.2 3 1.2 47 53 40 43 26 17 55 11 71 65 80 0.6 50 375 54 55 375 450 1.6 MIN & MAX RATINGS Min 1000 13.8 -0.6 14.9 +0.6 3 Max MHz MHz dB dB ps dB dB dB dB dB dB ps ps ns % ns -dBc -dBc -dBc -dBc +dBm dB dB dB dB 280 2.0 250 625 60 A A/C mV V/C mA dB IBN IBN ICC PSRR SSBW SSBW LPD GD RINI RIIN UNITS SYM
CONDITIONS KH104AI 0dBm out 10dBm out @ 100MHz DC - 750MHz DC - 600MHz DC - 750MHz 750MHz - 1100MHz DC - 750MHz 750MHz - 1100MHz DC - 750MHz 750MHz - 1100MHz 1V step 2V step 1V step 1V step Vinpeak = 0.5V 0dBm, 100MHz 0dBm, 100MHz 10dBm, 100MHz 10dBm, 100MHz 100MHz 500MHz 10Hz to 1200MHz 100MHz 500MHz note 2 note 2 note 3 note 3 no load 1KHz
non-inverting gain (note 1) gain flatness linear phase deviation group delay reverse isolation input return loss output return loss
TIME DOMAIN RESPONSE rise and fall time (10% to 90%) settling time to 0.8% overshoot overload recovery NOISE AND DISTORTION RESPONSE 2nd harmonic distortion 3rd harmonic distortion 2nd harmonic distortion 3rd harmonic distortion 3rd order intermolulation intercept 2-tone, 1MHz separation equivalent input noise voltage noise figure usable dynamic range STATIC, DC PERFORMANCE input bias current input bias current (drift) output offset voltage output offset voltage (drift) * supply current supply rejection ratio
TRS TRL TS OS OR HD2 HD3 HD2 HD3
30 35
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.
Absolute Maximum Ratings
VCC Io input voltage junction temperature operating temperature storage temperature 9V to 16V 40mA 0.5V +175C AI: -25C to +85C -65C to +150C
Notes
1. Nominal gain only - gain variation over temperature is 0.1dB. 2. Input offset voltage = (input bias current) x (Rs || 50). 3. Output offset can be adjusted to zero with an external potentiometer - see "Reducing DC Offset". 4. * AI 100% tested at 25C. AI Sample tested at 25C.
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REV. 1A February 2001
KH104
DATA SHEET
KH104 Performance Characteristics (TA = +25C, VCC = 15V, RL = 50, Rs = 50; unless specified)
Forward Gain and Phase
16
Po = 0dBm |S21|
Reverse Gain and Phase
180 0
Po = 0dBm
Input Return Loss
360 0
14
|S12| (-dB)
12
-180
40
|S12|
|S11| (-dB)
S21
0
20
S12
180
20
S21 (deg)
S12 (deg)
|S21| (dB)
0
40
10
-360
60
-180
60
8 0 260 520 780 1.04G 1.3G
540
80 0 260 520 780 1.04G 1.3G
-360
80 0 260 520 780 1.04G 1.3G
Frequency (MHz) Output Return Loss
0
Frequency (MHz) Pulse Response
-20
Po = 0dBm
Frequency (MHz) 2nd and 3rd Harmonic Distortion
Input (40mV/div)
Distortion (dBc)
20
Input
-30
Output (200mV/div)
|S22| (-dB)
-40 -50
2nd
Output
40
-60
3rd
60
-70 80 0 260 520 780 1.04G 1.3G -80
500ps/div
100k
1M
10M
100M
1G
Frequency (MHz) 2-Tone, 3rd Order Intermod. Intercept
30 -120
Frequency (Hz) Noise Spectral Density
16
-1dB Gain Compression
Noise Level (dBm/Hz)
Intercept Point (dBm)
Power Output (dBm)
25 20 15 10 5 0 0 200 400 600 800 1000
-130 -140 -150 -160
12
8
4
-170 10 1k 100k 10M 1G
0 0 200 400 600 800 1000
Frequency (MHz) Usable Dynamic Range
72 70
Frequency (Hz) Power Supply Rejection Ratio
105
Frequency (MHz) Relative Bandwidth vs. Case Temp.
Relative Bandwidth (%)
Dynamic Range (dB)
70
60
100 95 90 85
Pd = 1.6W CA = 30C/W
66 64 62 60 0 200 400 600 800 1000
PSRR (dB)
68
50 40 30 20 10 1 10 100 1k 10k 100k 1M
80 0 20 40 60 80 100 120 140
Frequency (MHz)
Frequency (Hz)
Case Temperature (C)
REV. 1A February 2001
3
DATA SHEET
KH104
PC Board Layout Considerations Proper layout of printed circuit boards is important to achieve optimum performance of a circuit operating in the 1GHz frequency range. Use of microstripline is recommended for all signal-carrying paths and low resistance, low inductance signal return and bypass paths should be used. To keep the impedance of these paths low, use as much ground plane as possible. Ground plane also serves to increase the flow of heat out of the package. The KH104 has three types of connections: signal paths (input and output), DC inputs (supplies and offset adjust), and grounds. 50 microstrip is recommended for connection to the input (pin 4) and output (pin 11). Microstrip on a doublesided PC board consists of a ground plane on one side of the board and a constantwidth signal-carrying trace on the other side of the board. For 1/16" G10 or FR-4 PC board material, a 0.1" wide trace will have a 50 characteristic impedance. The ground plane beneath the signal trace must extend at least one trace width on either side of the trace. Also, all traces (including ground) should be kept at least one trace width from the signal carrying traces. To keep power supply noise and oscillations from appearing at the amplifier output, all supply pins should be capacitively bypassed to ground. The power supply pins (1 and 2) are the inputs to a pair of voltage regulators whose outputs are at pins 13 and 14. It is recommended that 0.01F or larger ceramic capacitors be connected from pins 1, 2, 13 and 14 to ground, within 0.2" of the pins. A 1F or larger solid tantalum capacitor to ground is required within 3" of pins 1 and 2, and for good low frequency performance, solid tantalum capacitors of at least 15F should be connected from pins 13 and 14 to ground within 3" of the pins. Use 0.025" or wider traces for the supply lines. The offset adjust pin (12) also requires bypassing; a 0.01F or larger ceramic capacitor to ground within 0.2" of the pin is recommended. Grounding is the final layout consideration. Pins 3 and 510 should all be connected to a ground plane which should cover as much of one side of the board around the amplifier as possible. Reducing DC Offset DC offset of the KH104 may be adjusted by applying a DC voltage to the amplifier's offset adjust pin (12). The simplest method is shown in Figure 1. Using this method of offset adjust it is possible to vary the output offset by approximately 400mV. This simple adjustment has no effect on the offset drift characteristics of the KH104.
+15V
39
0.01
+15V 2.2
10K Offset Adjust -15V Vin
0.01 0.01
12 4 3,5-10 14 1
KH104
2 13
11
Vo
0.01 2.2
Capacitance if F 39 0.01 -15V
Figure 1: Basic Circuit If lower offset and offset drift are required, a low frequency op amp may be used in conjunction with the KH104 in a composite configuration. The suggested circuit appears in Figure 2. Its method of operation is to compare an attenuated version of the output signal to the input signal and apply a correcting voltage at the offset adjust pin. A compensation capacitor Cs reduces the bandwidth of the op amp correction circuit to limit the op amp's effect on the KH104 to frequencies below f45, the frequency at which the op amp has 45dB of open loop gain. Using an LM108, f45 is about 7Hz with Cs = 0.1F. Thus the op amp can correct DC and low frequency errors below f45, without affecting KH104 performance above f45. Also note that the noise performance of the op amp will dominate below f45.
12 4
+15V
0.01 2k
7 2 6
Vin
KH104
11
Vo RL 50
49.9k 0.01 Rc 9.76k Ra 11.8k Rb 1k
Capacitance in F Rc = (Ra + Rb ) || 49.9k
LM108
8 4
3
Cs 0.01
0.01
-15V
Figure 2: Composite Amplifier With an LM108 op amp in this composite configuration, input offset is typically 2mV and drift is 15mV/C. At frequencies well below f45, the composite gain is equal to (1 + 49.9k/(Ra + Rb)) and the output impedance is
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REV. 1A February 2001
KH104
DATA SHEET
very low. As the signal frequency increases beyond f45, the op amp loses influence and the KH104 gain and output impedance dominate. To ensure a smooth transition and matched gain at all frequencies, adjust Rb for a minimum op amp output swing with a 0.1Vpp sinewave input (to the KH104) at the frequency f45. Since the KH104 has a 50 output impedance, its output voltage is a function of the load impedance _ (Av ~ 10RL/(RL + 50)), whereas the gain of the composite amplifier at low frequencies and DC is relatively independent of the load impedance, due to the high open-loop gain of the op amp. Thus, to avoid gain mismatching and phase non-linearity, use the composite amplifier only if the load impedance is constant from DC to at least 10(f45). Use of a composite amplifier reduces input offset voltage and its corresponding drift, but has no effect on input bias current. This current is converted to an input voltage by the resistance to ground seen at the amplifier input and the voltage appears, amplified, at the output. Typical input offset voltage due to the bias current is 2mV and input offset drift is approximately 15mV/C. Thermal Considerations The KH104 case must be maintained at or below 140C. Note that because of the amplifier design, power dissipation remains fairly constant, independent of the load or drive level. Therefore, standard derating is not possible. There are two ways to keep the case temperature low. The first is to keep the amount of power dissipated inside the package to a minimum and the second is to get the heat out of the package quickly by reducing the thermal resistance from case to ambient. A large portion of the heat dissipated inside the package is in the voltage regulators. At the minimum +9V supply level the regulators dissipate 390mW and at the maximum 16V supply level they dissipate 1.2W. The amplifier itself dissipates a fairly constant 600mW (55mA x 10.8V). Reducing the power dissipation of the internal regulators will go far towards reducing the internal junction temperatures without impacting the so performance. Reducing either the input supply voltages (on pins 1 and 2) and/or shunting the regulator current through external resistors (from pins 1 to 14 and pins 2 to 13) are both effective means towards significantly reducing the internal power dissipation. A minimum
voltage across the regulator of 3.6V and a minimum regulator current of 10mA will satisfy the regulator dropout voltage and current limits. Given the maximum anticipated power supply voltages, the shunt resistor should be calculated to yield a 35mA current from that voltage to the regulated voltage of 5.4V. This will leave 10mA through the regulator at the minimum quiescent current of 45mA. The regulator input voltages may be reduced directly by dropping the voltage supplies, or, if that option is not available, using either a zener or resistive dropping element in series with the supply. If a series dropping element is used, the decoupling capacitors must appear on pins 1 and 2 of the KH104. Figure 3 shows two possible power reduction circuits from fixed 15V supplies. Several methods of decreasing the thermal resistance from case to ambient are possible. With no heat paths other than still air at 25C, the thermal resistance from case to ambient for the KH104 is about 40C/W. When placed in a printed circuit board with all ground pins soldered into a ground plane 1" X 1.5", the thermal resistance drops to about 30C/W In this configuration, the case rise will be 30C for 9V supplies and 50C for 16V supplies. This results in maximum allowable ambient temperatures of 110C and 90C, respectively. If higher operating temperatures are required, heat sinking of the package is recommended.
+15V D1 5.6V 2.2F + 0.01F
1
+15V 60 2.2F + 0.01F
1 14 13
115
200
Vin
2
Vo
Vin
2
14 13
Vo
115
200
2.2F
+
0.01F
D2 5.6V
2.2F
+
0.01F 60 -15V
-15V D1, D2 IN4734 nominal, no load Pd ~ 760mW -
nominal, no load Pd ~ 900mW -
Figure 3: Reducing Power Dissipation
REV. 1A February 2001
5
DATA SHEET
KH104
KH104 Package Dimensions
0.140 - 0.180 (3.56 - 4.57) 0.060 R (TYP) 0.740 - 0.760 (18.80 - 19.30) 0.016 - 0.020 (0.41 - 0.51)
0.240 - 0.260 (6.10 - 6.60) 0.090 - 0.110 (2.29 - 2.79) 0.590 - 0.610 (14.99 - 15.49)
0.740 - 0.760 (18.80 - 19.30)
0.590 - 0.610 (14.99 - 15.49)
0.050 R (TYP)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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(c) 2001 Fairchild Semiconductor Corporation
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